Aspects of the present invention are directed to gate structures having at least partial silicidation.
In typical complementary-metal-oxide-semiconductor (CMOS) transistors, metal contacts and polysilicon gates have pitches that have become increasingly small over time as spatial and power requirements have evolved. As device pitch has decreased, a need to produce smaller and smaller spaces between metal contacts and polysilicon gates has become increasingly important. However, producing small spaces using the current photolithography alignment processes has proven to be prone to short circuits and other similar failures.
A short circuit in a gate structure may be caused, in some cases, by the contact vias at one of the source or the drain region contacting the gate. This is especially likely where the gate pitch is relatively small. One solution to this problem has been to fully encapsulate the gate to thereby prevent contact between the gate and the contact vias. Unfortunately, this solution results in the gate structure as a whole having a very high gate resistance and slow switch timing. In a memory device, which does not require fast switching capability, this is less of a drawback. However, in a logic device, which requires fast switching capability, fully encapsulated gate structures are less useful.